The present invention relates generally to electronic circuits and more particularly to a method and apparatus for circuit power-down.
Power consumption is a key performance characteristic in electronic circuits. Low power consumption is desirable due to low heat dissipation and low power supply requirements.
A problem in electronic circuit design is that sometimes portions of an electronic circuit are not used for given period of time yet they still consume power during that time. Therefore, it is desirable to reduce the power consumption of unused portions of an electronic circuit for certain periods of time.
Techniques to reduce the power consumption of unused portions of an electronic circuit are known to exist. One such technique is a circuit arrangement for reducing a reference supply voltage level of a reference generator for an ECL circuit during a power-down mode. A first switching network is connected to the input of a reference generator for disabling the input of the reference generator in response to a control signal so as to reduce the level of the reference supply voltage. A second switching network is connected to the output of the reference generator for disabling the output of the reference generator in response to the control signal.
It is common to use transistors as switches to connect or disconnect two signal nodes so as to control the passage of ac and dc signals between the two nodes. Examples of such switches are bipolar, JFET or MOS switches.
When bipolar or JFET transistors are used, the control node of the transistors generally has low impedance to the signal nodes being switched so it must be allowed to follow the signal with minimum effect (i.e. with minimum ac current injection). This is to say it must have high a.c. impedance or it must have the a.c. signal specifically superimposed on any d.c. voltages needed for control. Such control techniques are known for bipolar and JFET switches.
When MOS transistors are used as switches, however, the situation is more complex because an alternate scheme is often used. With this scheme the controlling gate is connected to a sufficiently high potential to ensure the transistor will remain well turned on for the full range of signals to be switched, and the high impedance of the MOS gate prevents excessive loading of the signal. When very high frequency ac signals are involved, however, the capacitance between the channel and the gate of the MOS switch represent sufficiently low impedance to be a serious issue.
The known power-down techniques are deficient in that they affect the circuit performance during powered conditions and fail to reduce the power consumption of a circuit by an adequate amount.
Accordingly, there is a need to adequately power-down a circuit with minimal impact on circuit performance during powered conditions.
The present invention is directed to an apparatus for circuit power-down with minimal impact on circuit performance during powered conditions.
According to one aspect of the present invention, there is provided an apparatus for circuit power-down including a bias block switching means, a first switch, a first switched constant current means and a first voltage follower. The bias block switching means has a first node, second node and a third node. The bias block switching means has a first state for electrically connecting the first node and the third node and a second state for electrically connecting the second node and the third node. The bias block switching means is responsive to a power down control signal for switching between the first state of the bias block switching means the second state of the bias block switching means. The first node of the bias block switching means is operatively coupled to a reference voltage and the second node of the bias block switching means is operatively coupled to a first supply voltage. The first switch has a first node and a second node. The first switch has a first state for electrically isolating the first node and the second node and a second state for electrically connecting the first node and the second node. The first switch is responsive to the power down control signal for switching between the first state of the first switch and the second state of the first switch. The first node of the first switch provides the output signal. The first switched constant current means is coupled to the first node of the first switch and the first supply voltage. The first switched constant current means has a first state for providing a constant current output and a second state for providing substantially no current. The first switched constant current means is responsive to a bias signal for switching between the first state of the first switched constant current means and the second state of the first switched constant current means. The bias signal is output from the third node of the bias block switch. The first voltage follower has a first terminal, a second terminal and a third terminal. The first terminal receives the input signal, the second terminal is operatively coupled to the second voltage supply and the third terminal is operatively coupled to the second node of the first switch.
An advantage of the invention is that it only permits parasitic current during power-down operation.
Other aspect and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures.